1. Field of the Invention
This invention pertains generally to semiconductor memory, and more particularly to static random access memory circuits.
2. Description of Related Art
Static Random Access Memory (SRAM) is a form of electronic data storage which retains data as long as power is supplied. Static RAMs are widely utilized within all manner of electronic devices, and are particularly well-suited for use in portable or hand-held applications, as well as in high performance device applications. In portable or hand-held device applications, such as cell phones, SRAMs provide stable data retention without support circuits, thus keeping complexity low while providing robust data retention. In high performance applications, such as microprocessor caching, since the SRAM can provide fast access times while not requiring the cell data refresh operations required in Dynamic Random Access Memory (DRAM).
FIG. 1 shows a typical SRAM cell consisting of six transistors (6T SRAM) and related peripheral circuits. For example, when node C_j is precharged at Vdd (data H), mp2_j is turned off and mn2_j is turned on. Node CB_j is set Vss (data L). Therefore, mp1_j is turned on and mn1_j is turned off. Hence, as long as power is supplied, data at C and CB are maintained high and low respectively.
FIG. 2 shows a read timing diagram of the conventional 6T SRAM cell shown in FIG. 1. In a precharge cycle, PPREi is at logic low and mpp1_i and mpp2_i are turned on. So, bit line pairs (BL_i and BLB_i) are precharged at Vdd, logic high. When a word line (WL_i) is enabled, a bit line is discharged depending on the stored data. For example, node C_j is high and CB_j is low. According to the word line enabling, mn3_j and mn4_j are turned on. Since CB_j is low and mn2_j is turned on, the voltage of BLBi is discharged slowly through mn4_j and mn2_j. When a certain amount of voltage difference between bit line pairs arises, a sensing enable signal (PSAEi) is enabled to amplify the signal difference. The voltage difference on the bit line pairs is amplified by the sense amplifier (i) and a full CMOS output pairs (Di and Dbi) are generated at the outputs of the sense amplifier.
Since the typical 6T SRAM cell creates a signal difference on bit lines by itself, the read speed of SRAM is faster than that of DRAM, in which a charge sharing time between the bit line and cell capacitances is needed and read speed is slowed. This 6T SRAM cell has a very stable structure and is widely used in typical SRAM design. However, there is a trade-off between power consumption and read speed. As the minimum feature size (i.e. design rule) decreases and the threshold voltage of transistors is reduced to maintain performance as operating voltage is lowered, the leakage current (i.e. standby current) becomes an important factor. In this example, since C_j is at a high level and CB_j is at a low level, mp2_j and mn1_j are turned off. Even though these two transistors are in an off state, there is a current flowing through the devices referred to as a cell leakage current. At 0.18 μm technology, this leakage current is on the order of fA (10e−15) and can be substantially ignored for most applications.
However, with regard to more advanced technology such as 0.13 μm technology, since this current is then on the order of tens of nA (10e−9), the level of current can no longer be ignored. For example, for a 16 Mb SRAM, when a cell leakage current is about 10 nA, the total current is 16*1024*1024*10*1e−9=16 mA. This level of leakage current equates to a large portion of the total power consumption for the device. It should also be appreciated that this leakage current is temperature dependent, increasing in response increasing temperature. For more advanced technology such as 0.11 μm technology, the cell leakage current increases significantly. Therefore, the power consumption component which arises as a result of cell leakage current becomes quite substantial. As the systems relying on SRAM become increasingly complex, the density of SRAM will continue to increase, and the total power consumed by cell leakage currents based on conventional SRAM architectures will continue to increase.
As mentioned earlier, there is a trade-off to be made between power consumption and cell read speed. Since the cell read speed is determined by how fast a bit line node (e.g., CB_j) is discharged through the cell pull-down transistor (mn1_j or mn2_j). Therefore, the sizes of the cell access transistor (mn3_j or mn4_j) and the cell pull-down transistor (mn1_j or mn2_j) need to increase to enhance the read speed. However, when these cell access transistors and cell pull-down transistors increase in size, leakage currents flowing through these transistors also increase. In this example, when these transistors increase in size, leakage current flowing through a pair of mn4_j and mn2_j and mn1_j increases. Therefore, a trade-off between the cell leakage current and the cell read time makes SRAM design complicated and difficult as the operating voltage goes down.
In general, two classes of SRAM cells are implemented depending on the whether the SRAM is used with a low power or high performance application. With regard to low power applications, such as low power hand-held devices, the stand-by current (i.e. power consumption while the chip is in a stand-by mode), is often the most important consideration as these low power portable applications often rely on battery operation wherein stand-by current is a major determiner of battery life. This is in contrast to high performance applications such as cache memory, wherein cell data read speed is of critical importance. However, due to a drastic increase of the cell leakage current, the conventional 6T SRAM cell structure is facing a technical barrier to meet the design requirement. When device sizes increase and the threshold voltage of transistors decreases to meet the required speed, the power consumption due to the cell leakage current is a concern. When device sizes are scaled down and the threshold voltage of transistors increases to suppress leakage current, the cell read speed is degraded due to reduced current driving capability of the cell access and pull-down transistors.
Accordingly, a need exists for advanced SRAM circuits and methods for reducing leakage currents without sacrificing read speed. The present invention fulfills that need and others, while overcoming the drawbacks found in conventional SRAM architectures.